1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and in particular to a method for forming an interconnection of a semiconductor device having a low resistance.
The present invention also relates to an interconnection of a semiconductor device having low resistance.
2. Description of the Background Art
FIG. 1 is a graph illustrating the variation of line resistance as a function of the line width of an interconnection of a semiconductor device.
The X axis and the Y axis depict the line width and line resistance values of the interconnection, respectively. Plot xe2x80x9cAxe2x80x9d shows the resistance of a polycide interconnection formed by stacking a tungsten silicide layer on pure, undoped polysilicon, and plot xe2x80x9cBxe2x80x9d shows the resistance of a polycide interconnection formed by stacking the tungsten silicide layer on doped polysilicon. The tungsten silicide layer is of tetragonal crystal structure and is deposited by a chemical vapor deposition process and annealed.
In plots A and B, the thickness of the polysilicon layer and tungsten silicide layer which are deposited is 1000 xc3x85 and 1500 xc3x85, respectively. The annealing process is carried out on the tungsten silicide layer at a temperature of 1000xc2x0 C. for 30 seconds.
As is apparent from FIG. 1, the resistance of the interconnection is lower when the doped polysilicon is used, as in plot B, than when the pure polysilicon is employed, as in plot A.
FIGS. 2A to 2D are cross-sectional views illustrating sequential steps of a method for forming an interconnection of a semiconductor device in accordance with a first example of the conventional art.
Referring to FIG. 2A, a first insulation layer (gate oxide film) 2 is formed on a semiconductor substrate 1, and a semiconductor layer 3 and a first tungsten silicide layer 4 are sequentially deposited on the first insulation layer 2.
The first insulation layer is a silicon oxide film formed in accordance with a thermal oxidation or chemical vapor deposition process. The semiconductor layer 3 consists of a doped polysilicon layer, and the first tungsten silicide layer 4 is deposited according to a chemical vapor deposition process.
As illustrated in FIG. 2B, a second tungsten silicide layer 5, having a tetragonal crystal structure, is formed by annealing the first tungsten silicide layer 4 at a high temperature. As a result, the interface between the semiconductor layer 3 and the second tungsten silicide layer 5 becomes uneven. This occurs because silicon of the semiconductor layer 3 diffuses into the first tungsten silicide layer 4.
As shown in FIG. 2C, an etching mask 6 is formed in order to define an interconnection. The etching mask 6 is formed by sequentially stacking a second insulation layer 6a and a third insulation layer 6b on the second tungsten silicide layer 5, and by etching and patterning the stacked layers by using a photoresist pattern.
The second insulation layer 6a consists of silicon oxide SiO2, and the third insulation layer 6b consists of silicon nitride Si3N4.
Referring to FIG. 2D, the second tungsten silicide layer 5, the semiconductor layer 3 and the first insulation layer 2 are selectively etched and removed by using the etching.mask 6, thereby finishing the conventional process for forming an interconnection of a semiconductor device.
The above-described method for forming an interconnection of a semiconductor device has a disadvantage in that the interface between the semiconductor layer 3 and the tungsten silicide layer 5 becomes uneven, and thus, during the etching process for forming the interconnection, a residual 9 (refer to FIG. 2D) of the tungsten siuicide layer 5 or the semiconductor layer 3 remains on the insulation layer 2, thereby causing damage of the insulation layer 2 and reducing the reliability of the semiconductor device.
Another example of a conventional method for forming an interconnection of a semiconductor device will now be described with reference to FIGS. 3a to 3C.
As shown in FIG. 3A, an impurity region 11 is formed in a predetermined portion of a semiconductor substrate 10. An insulation layer 12 is formed on the semiconductor substrate 10. The insulation layer 12 is etched so that an upper surface of the impurity region 11 can be exposed, thereby forming a contact hole 12A. Thereafter, a semiconductor layer 13 is formed at the upper surface of the insulation layer 12, and inner walls and bottom surface of the contact hole 12a. A first tungsten silicide layer 14 is formed on the semiconductor layer 13.
The insulation layer 12 consists of one of borophosphosilicate glass (BPSG), spin-on glass (SOG) and plasma-enhanced tetraethylorthosilicate (PE-TEOS). The semiconductor layer 13 consists of a p-type or n-type doped polysilicon layer. The first tungsten silicide layer 14 is formed according to a chemical vapor deposition process.
Referring to FIG. 3B, a second tungsten silicide layer 15, of a tetragonal crystal structure and having a low resistance, is formed by annealing the first tungsten silicide layer 14. Accordingly, the interface between the semiconductor layer 13 and the second tungsten silicide layer 15 becomes uneven. This occurs because silicon of the semiconductor layer 13 diffuses into the first tungsten silicide layer 14 during the annealing process.
As illustrated in FIG. 3C, the semiconductor layer 13 and the second tungsten silicide layer 15 on the insulation layer 12 are removed according to a chemical mechanical polishing (CMP) process or etching process so that the upper portion of the insulation film 12 can be exposed. As a result, the second tungsten silicide layer 15 and the semiconductor layer 13 remain only in the contact hole 12A, thereby finishing the conventional method for forming an interconnection of a semiconductor device.
As described above in relation to the first example of a conventional method, this second example of a conventional method for forming an interconnection of a semiconductor device has a disadvantage in that the interface between the semiconductor layer 13 and the tungsten silicide layer 15 is uneven. Thus, during the etching or CMP process for forming the interconnection, a residual 19 (refer to FIG. 3C) of the tungsten silicide layer 15 or semiconductor layer 13 remains on the insulation layer 12, thereby causing a bridge among interconnections or damage of the insulation layer 12, and reducing the reliability of the semiconductor device.
Accordingly, it is an object of the present invention to provide a method for forming an interconnection of a semiconductor device which can improve reliability by positioning a barrier metal layer between a semiconductor layer and a tungsten silicide layer.
In order to achieve the above-described object of the present invention, there is provided a method for forming an interconnection of a semiconductor device in accordance with a first embodiment of the present invention, including: forming a first insulation layer over a semiconductor substrate, forming a first semiconductor layer over the first insulation layer, forming a barrier metal layer over the first semiconductor layer, forming a second semiconductor layer over the barrier metal layer, forming an amorphous first tungsten silicide layer over the second semiconductor layer, annealing the amorphous first tungsten silicide layer to form a second tungsten silicide layer having a tetragonal crystal structure, forming an etching mask over the second tungsten silicide layer in order to define the interconnection, and etching the second tungsten silicide layer, the second semiconductor layer, the barrier metal layer and the first semiconductor layer sequentially and preferentially by employing the etching mask.
There is also provided a method for forming an interconnection of a semiconductor device in accordance with a second embodiment of the present invention, including: providing a semiconductor substrate having an impurity region at its surface, forming an insulation layer having a contact hole over the impurity region, forming a first semiconductor layer at inner walls and a bottom surface of the contact hole and over the insulation layer, forming a barrier metal layer over the first semiconductor layer, forming a second semiconductor layer over the barrier metal layer, forming an amorphous first tungsten silicide layer over the second semiconductor layer, annealing the amorphous first tungsten silicide layer to form a second tungsten silicide layer having a tetragonal crystal structure, and etching back the second tungsten silicide layer, the second semiconductor layer, the barrier metal layer and the first semiconductor layer sequentially and selectively so that an upper portion of the insulation layer can be exposed.
It is also an object of the present invention to provide an interconnection of a semiconductor device made up of a first insulation layer formed over a semiconductor substrate, a first semiconductor layer formed over a portion of the first insulation layer, a barrier metal layer formed over the first semiconductor layer, a second semiconductor layer formed over the barrier metal layer, and a tungsten silicide layer having a tetragonal crystal structure formed over the second semiconductor layer.
There is also provided an interconnection of a semiconductor device made up of a semiconductor substrate having an impurity region at its surface, an insulation layer formed over the semiconductor substrate having a contact hole over the impurity region, a first semiconductor layer formed at inner walls and a bottom surface of the contact hole, a barrier metal layer formed over the first semiconductor layer, a second semiconductor layer formed over the barrier metal layer, and a tungsten silicide layer having a tetragonal crystal structure formed over the second semiconductor layer.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.